How to use an additionnal UART in a Pynq-based system running on Zedboard

This tutorial shows how to add an additional UART module on a PYNQ-based system only by modifying the programmable logic (PL) part of a Zynq system. The tutorial was applied on a Zedboard platform running Pynq 2.4 image.


First of all, you need to have a working PYNQ-based system. This tutorial can be applied on any PYNQ-based system. For instance, on a Pynq-Z1 platform the base overlay

Overlay building

  • Start Vivado tool. I used Vivado 2017.4 but any other version can be used to generate the bitstream of the overlay.
  • Create an RTL project.
  • In a block design, instantiate Zynq PS system. Run Automation tool to build the basic Zynq-based system.
  • From the IP catalog, add UART AXI lite module. Run again Automation tool to connect the instantiated axi-based uart to the PS.
  • By default, the baud rate is 9600. Right click on the module and adapt the values to your project. In my case, I chose the baud rate of 115200, no parity, ho hardware control.
  • Add a constraint file constraints.xdc with the pin assignments for RX and TX. On Zedboard, I chose JB PMOD port for UART connections: JB1 connected to W11 and JB2 connected to W12.
  • Create an HDL-wrapper of your design.
  • Run synthesize, implementation and generate bistream phases. Wait until the bitsream is generated.
  • Export the block design you create by File->Export->Export Block Design
  • Rename the generated design_1.tcl and design_1_wrapper_hdl.bit to uart.bit and uart.tcl

UART IP using in PYNQ

  • Connect to your Zedboard through Samba and copy uart.bit and uart.tcl to the pynq overlay folder
  • Connect to your platform via browser via
  • Download the uart custom overlay to the Zedboard PL part
  • By ussing mmio package and the memory addresses we can access to the RX and TX data.
Slavisa Jovanovic
Slavisa Jovanovic
Associate Professor (Maitre de conférence HDR)

My research interests include circuits and systems for AI and energy harvesting circuits.